1. Field of the Invention
The present invention generally relates to the design of integrated circuits and packaging for semiconductor chips, and more particularly to a method of assigning voltage domains (power and ground) to contacts of a chip carrier or interconnect.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
As the size of integrated circuits continues to shrink, and pin densities grow, it becomes increasingly more difficult to interconnect the chip to external circuitry. Chips are commonly attached to a substrate, e.g., a printed circuit board (PCB) using a carrier or package which fans out the connections to pads or pins on the PCB. FIG. 1 illustrates a typical chip assembly which includes an IC chip 1, a package 2, a PCB 3, and miscellaneous components such as capacitors 4. These various elements may be electrically coupled using surface-mount connections with C4 solder ball arrays 5. IC chip 1 is connected to package 2 which is in turn connected to PCB 3. Package 2 and PCB 3 both have multiple horizontal layers interconnected by vertical vias. A single layer may contain multiple planes, i.e., some for wiring and others for an electrical ground plane or a power plane. A given plane in package 2 may have multiple connections to the top and bottom surfaces to couple ground or power planes of IC chip 1 to ground or power planes of PCB 3. It is common to find 24 or more levels of wiring within a package.
The package itself can significantly affect the performance of the integrated circuit it supports, particularly as power supply currents, power densities, and operating frequencies increase. In addition to shrinking feature sizes and advances in lithography in CMOS technology that have increased circuit integration density (and thereby power density), there has also been a reduction in the chip's operating nominal voltage. These factors have progressively made it more difficult to deliver clean and controlled power to IC chips, and power delivery is often the most critical parameter in a system design. Decreasing channel widths are further leading to an exponential increase is leakage currents.
To more efficiently optimize leakage and power consumption on the chip, some chips are being partitioned into multiple voltage domains. However, partitioning in this manner requires the different voltages to be controlled very tightly which results in major constraints on the chip carrier design. The parameters of concern include the voltage gradients available at the circuits across the chip and pin current magnitudes at the carrier/PCB interface, all of which should ideally be minimized. Optimization is even more difficult with complex circuits like microprocessor chips that integrate one or more CPU (central processing unit) cores, input/output (I/O) interfaces, memory control units and several other functional units into one chip. Each of these building blocks are designed to meet their performance targets and are built with appropriate transistor types and circuit densities which causes a high power density variation across the chip area. In particular, the cores (which have a very high circuit density) typically have a much higher power demand compared to the rest of the functional units and are more sensitive to DC-drop (gradient) and current density.
Unfortunately, state-of-the-art chip carrier designs for single or multi-chip modules (SCM/MCM) are typically designed using a homogenous pattern for the bottom-side metallization (BSM) pins with no consideration given to circuit or power densities. When calculating the required power vias/pins for each voltage domain, the projected total current is simply divided by the maximum allowed pin/via current; the chip power density floorplan is not taken into account. As a result, the expected maximum pin current is higher than the calculated average current by a factor of 3-4. It would, therefore, be desirable to devise an improved technique for delivering power to an integrated circuit chip which could reduce DC gradients across the chip and power dissipation on the chip carrier. It would be further advantageous if the technique could reduce the maximum pin currents at the carrier/PCB interface.